PYNQ-z2的学习过程

1. PYNQ-Z2 如图：先学习10分钟轻松上手PYNQ （http://www.digilent.com.cn/studyinfo/67.html）这个是z1的不过都能学习，大致差不多。

视频内容如下：

PYNQ-Z2 映像文件img 写入SDcard，http://www.pynq.io/board 可以找到img

setup:

https://pynq.readthedocs.io/en/v2.6.1/getting_started/pynq_z2_setup.html

学习过程安装网站http://www.digilent.com.cn/community/411.html

通过 PYNQ，用户可以使用 Python 进行 APSoC 编程，并且代码可直接在 PYNQ-Z2 上进行开发和测试。通过 PYNQ，可编程逻辑电路将作为硬件库导入并通过其 API 进行编程，其方式与导入和编程软件库基本相同。

开源工具Win32diskimager可以将原始磁盘映像写入可移动设备中

../_images/pynqz2_setup.png

Set the ** Boot** jumper to the SD position. (This sets the board to boot from the Micro-SD card) -- 上图中标1的地方注意跳帽是蓝色位置 jp1
To power the board from the micro USB cable, set the Power jumper to the USB position. (You can also power the board from an external 12V power regulator by setting the jumper to REG.)-- 上图中标2的地方注意跳帽是蓝色位置
Insert the Micro SD card loaded with the PYNQ-Z2 image into the Micro SD card slot underneath the board--标3的地方
Connect the USB cable to your PC/Laptop, and to the PROG - UART MicroUSB port on the board--注意是标6的地方
Connect the Ethernet port by following the instructions below--标5的地方
Turn on the PYNQ-Z2 and check the boot sequence by following the instructions below--标6地方开关拨到on

Connect directly to a computer (Static IP):

Assign your computer a static IP address
Connect the board to your computer’s Ethernet port
Browse to http://192.168.2.99

Once your board is setup, to connect to Jupyter Notebooks open a web browser and navigate to:

http://192.168.2.99 If your board is connected to a computer via a static IP address

If your board is configured correctly you will be presented with a login screen. The username is xilinx and the password is also xilinx.

时钟：

PYNQ-Z2 provides a 50 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the PS subsystems. The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz.

The PYNQ-Z2 also has an external 125 MHz reference clock connected to pin H16 of the PL. The external reference clock allows the PL to be used independently of the PS.

Note that the reference clock output from the Ethernet PHY is used as the 125 MHz reference clock to the PL. When the PHYRSTB signal is driven low, the Ethernet PHY (U5) is held in reset disabling the CLK125.